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Logic Gates

All Basic Gates (NOT, AND, OR)

NOT Gate: 

Basic Memory Element: Using a feedback loop with NOT gates, a basic memory element can be aerated. It is called a bistable multivibrator.

If A = 0, 0 is in a stable state and

If A = 1, 1 is in a stable state.

But, an astable multivibrator creates a random sequence of 0s and 1s. (Depending on i/p)

If there are ‘n’ NOT gates  connected in a feedback path and n = Odd; if ${\mathbf{t}}_{\mathbf{pd}}$ represents the propagation delay of one NOT gate, then

Important note:

1) If the number of NOT gates is odd in a feedback path ⇒ Astable multivibrator

2) If the number of NOT gates is even in a feedback path ⇒ Bistable multivibrator

Example 1:

Consider the following circuit with a propagation delay of 100 ps (PS = pico second) = ${10}^{-12}$ seconds) (${\mathrm{t}}_{\mathrm{pd}}$ of each NOT gate is loops). Calculate the time period and frequency.

Solution:

Example 2:

Consider the following circuit. Calculate the time period. 

Solution:

Time period and frequency depend on the number of NOT gates involved in feedback only. Other gates will cause delay only.

∴ Time period = (3 X 10 X 2) = 60 s

AND Gate:

AND gate follows Commutative and associative law.

1) AB = BA

2) A(BC) = (AB)C

Enable input of AND Gate:

During enable situation AND gate act as a buffer.

Disable input of AND gate

Question:

What should be the output of the circuit if z represents the floating input of AND gate?

Solution:

Floating input is always enable i/p for AND gate, which is 1. (So, z = 1)

So, the output is 0.

OR Gate:

OR gate follows Commutative and associative law.

1) A+B = B+A

2) A+(B+C) = (A+B)+C

Just in the inverse logic as shown in AND,

i) Enable i/p of OR Gate= 0 (behaves as a buffer)

ii) Disable i/p of OR gate = 1