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- Introduction: OS
- Booting Process
- Command Interpreter
- Dual mode of operation
- System Calls
- Difference between system call and library call
- Interrupt and Trap
- Introduction
- Scheduling Criteria, Terms and Concepts
- Different Type Scheduling Algorithms
- Longest Job First
- Longest Remaining Time First
- Highest Response Ratio Next (HRRN)
- Priority Scheduling
- Least Completed Next (LCN) Scheduling
- Multi-Level Queue Scheduling
- Multilevel Feedback Queue Scheduling
- Guaranteed Scheduling
- Fair Share Scheduling
- Lottery Scheduling
- Multi-Processor Scheduling
- Deadline Scheduling
- Rate-Monotonic Scheduling
- POSIX Real-Time Scheduling
- Priority Inversion
- Proportional Share Scheduling
- Comparison table of Scheduling Algorithm
- Algorithm Evaluation for Scheduling
- Important concept of MM
- Memory Representation as Address
- Memory layout for a Process
- Logical and Physical Address Space
- Necessity of Memory Management
- Introduction
- Concept of Non-contiguous memory allocation
- Basic concept of Paging
- Address Translation
- Process of Paging Method
- Calculation of Offset for paging
- Calculation of Logical Address Bit and number of Pages
- Calculation of Physical Address Bit and number of Frames
- Calculation of Page Table Size
- Organization of MMU
- Why Page size power of 2
- Paging Address Calculation: example1
- Paging Numeric Problem: Example2
- Paging Address Calculation: Example3
- Paging Address Calculation: Question1
- Some Important Question 2
- Paging Address Translation: Question3
- UGC NET Paging Question
- GATE Paging Question
- Number of information at Page Entry
- Exams Question on Page Entry Information
- Exam Question: Page Entry Information
- Calculates Page Table Entry Size
- Calculates Page Size
- Calculation of Optimal Page Size
- Question on Optimal Page Size
- Hashed Page Table with Example
- Inverted Page Table with Gate Question
- Question on Inverted Page Table
- Multi-Level Paging
- Multi-level paging: Example1
- Multi-level paging: Example2
- Allocation of Frames
- Subject Mock
Address Translation:
Important note: This chapter is very important for examination GATE/NET/SET/Engineering/Degree Courses.
Address Translation
When the CPU tries to fetch a word or data from the main memory, the CPU generates a Logical address (Relocatable address) for this word or data but this address is not the actual location of the memory. Memory Management Unit (MMU) converts the Logical address (Relocatable address) to the corresponding Physical address (Absolute address) to map the actual location of main memory for this word or data.
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Here logical address contains two parts: page number and Offset
and physical address contains two parts: frame number and Offset
Page table and Pages both reside in the main memory.
Offset
Here offset is the same for logical address and physical address space because offset means particular which word CPU wants to get from main memory.
So, logical address to physical address conversion means only convert page number to frame number.
Apart from the logical address CPU provides two more information to MMU
1. Page Table Base Register (PTBR): It gives you the base address of the memory of the page table.
2. Page Table length Register (PTLR): It indicates the size of the table.
# Offset is the same for both page number and frame number. From the offset, MMU gets to know which word CPU wants from the memory location.
# So, conversion of the logical address to physical address means only converts page number to frame number because the offset is the same for both cases.
