CREATE OWN LIBRARY

Design circuit with Minimum NAND gate

Before seeing the chapter please follow the previous chapter: 

Design circuit with Minimum NAND and NOR gate, Important points

Let consider some questions to understand how to design a circuit using the minimum NAND gate.

Question 1: 

Solution:

First design circuit simple way.

We require simple two AND and one NOT.

Now, how many NAND gates require implementing AND that is 2 and NAND gate require for NOT i.e. 1.

Question 2:

How many 2 input minimum of NAND requires to implement AB + CD.

Solution:

4 NAND for 2 AND gate and 3 NAND gate for one (1) OR gate.

So, a total of 7 NAND gates require.

But the answer is wrong.

It is wrong because we need the minimum number of NAND gates. We can design the circuit by 7 NAND gate but it is not minimum.

Now we can design the circuit but in a different way:

Two NOT will be canceled. So, we can use and as we know double bubble OR means NAND.

So, we can design the circuit as:

So, we require a minimum of 3 NAND gates to implement the expression AB + CD.

If we have this type of circuit where two levels of AND – OR hierarchy then it is easily converted by NAND.

So, the concept: If the circuit in form SOP which two levels of AND – OR hierarchy, Then we can put not a bubble in two levels of ‘AND’ and then cancel it by putting double bubble at OR gate.

And we know we design this above circuit as: 

Because SOP means Sum Of Product. So, the two-level AND OR hierarchy is SOP.

And this type of hierarchy circuit easily convertible by NAND. 

Important note:

When we get any expression, it can convert in SOP form after that it will be easier to implement it by the minimum number of NAND.