FOR FREE CONTENT
- Introduction: OS
- Booting Process
- Command Interpreter
- Dual mode of operation
- System Calls
- Difference between system call and library call
- Interrupt and Trap
- Introduction
- Scheduling Criteria, Terms and Concepts
- Different Type Scheduling Algorithms
- Longest Job First
- Longest Remaining Time First
- Highest Response Ratio Next (HRRN)
- Priority Scheduling
- Least Completed Next (LCN) Scheduling
- Multi-Level Queue Scheduling
- Multilevel Feedback Queue Scheduling
- Guaranteed Scheduling
- Fair Share Scheduling
- Lottery Scheduling
- Multi-Processor Scheduling
- Deadline Scheduling
- Rate-Monotonic Scheduling
- POSIX Real-Time Scheduling
- Priority Inversion
- Proportional Share Scheduling
- Comparison table of Scheduling Algorithm
- Algorithm Evaluation for Scheduling
- Important concept of MM
- Memory Representation as Address
- Memory layout for a Process
- Logical and Physical Address Space
- Necessity of Memory Management
- Introduction
- Concept of Non-contiguous memory allocation
- Basic concept of Paging
- Address Translation
- Process of Paging Method
- Calculation of Offset for paging
- Calculation of Logical Address Bit and number of Pages
- Calculation of Physical Address Bit and number of Frames
- Calculation of Page Table Size
- Organization of MMU
- Why Page size power of 2
- Paging Address Calculation: example1
- Paging Numeric Problem: Example2
- Paging Address Calculation: Example3
- Paging Address Calculation: Question1
- Some Important Question 2
- Paging Address Translation: Question3
- UGC NET Paging Question
- GATE Paging Question
- Number of information at Page Entry
- Exams Question on Page Entry Information
- Exam Question: Page Entry Information
- Calculates Page Table Entry Size
- Calculates Page Size
- Calculation of Optimal Page Size
- Question on Optimal Page Size
- Hashed Page Table with Example
- Inverted Page Table with Gate Question
- Question on Inverted Page Table
- Multi-Level Paging
- Multi-level paging: Example1
- Multi-level paging: Example2
- Allocation of Frames
- Subject Mock
Calculate Effective Access Time (EMAT)
Before this read chapter please follow the previous chapter first: Implementation of TLB
Effective Memory Access Time (EMAT) in two cases: TLB hit and TLB miss:
As we know process and page table both reside at the main memory, so when we access the page table we have to access the main memory it may be one memory reference or more than the memory reference as per the number of page tables used.
And we also know TLB has faster access time than main memory i.e.
TLB access time < Main memory access time.
Let, TBL access time = 30ns and memory access time = 100 ns
Effective Memory Access Time (EMAT) on TLB hit:
TLB hit: when we get page entry directly from TLB
EMAT = Access time of TLB to get page entry (frame number) + Access time of main memory to match frame number and get corresponding process page.
So, EMAT = 30ns + 100ns = 130ns
Note: In that case, we do not need to access the page table so, only one main memory reference is required.
Effective Memory Access Time (EMAT) on TLB miss:
TLB hit: When we do not get page entry at TLB and back to page table to get page entry.
EMAT = Access time to search TLB and not present + Access time of main memory for page table to get page entry (frame number) + Access time of main memory to match frame number and get corresponding process page.
So, EMAT = 30ns + 100ns + 100ns = 230ns
Note: Because we have to access one main memory additional for the page table, Effective Memory Access Time (EMAT) is going to increase. Here two main memory references are used.
At TLB miss, apart from accessing the page table to get frame number, we also load page entry from page table to TLB. But this loading time is negotiable.
Note: Please continue with Effective Access Time (EMAT) TLB hit and miss ratio: Effective Access Time using Hit ratio and Miss ratio
