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Implementation of TLB

Before this read chapter please follow the previous chapter first: Problem of Paging and solution

Locality of reference:

So, as we know the locality of reference, meaning that during any phase of execution, that process references only a relatively small number of the pages for a long time and few pages are kept on changing. But any point in time a process does not need entire pages in the main memory

Processes exhibit this behavior for two reasons:

Execution of instructions in a process is mostly sequential in nature because only 10 – 20 percent of instructions executed by a process are branch instructions. Processes also tend to perform similar operations on several elements of non-scalar data such as arrays. 

Due to the combined effect of these two reasons, instructions and data references made by a process tend to be in close proximity to previous instruction and data references made by it.

Translation Lookaside Buffer (TLB)

So, based on the locality of reference, to overcome this paging problem a high-speed cache is set up for page table entries called a Translate Lookaside Buffer (TLB) or associative memory. 

TLB is nothing but a special cache that keeps track of recently used transactions. It is usually inside the MMU and consists of a small number of entries like rarely more than 256.

So, here we translate logical address to physical address using TLB, without direct access to the page table.

Translate Logical Address to Physical Address using TLB:

TLB is the substitute for accessing page table but one thing is very important that TLB not contain entire page entries of page table TLB only contain those page entries that have been most recently and frequently used.

Whenever any page table entry refers to the first time which is not present at TLB, the system loads the page table entry in TLB.

TLB contains a TAG number for each page entry and by this tag number,  it searches that the required page entry is present in its TLB table for not.

First, the page number is extracted from the logical address (generated by CPU), and check with the entire tag number of TLB.

TLB Hit:

If the page number matches with any of the tag numbers then we will get the corresponding frame number directly from TLB and get the required word from the main memory using this frame number. This is called TLB hit.

So, in this case, we do not need to access the page table to get the frame number because we get the frame number from TLB which is faster than accessing the page table from memory.

TLB Miss:

As we know TLB does not contain all page entry of page table, only contains recently and frequently used page entry.

So, when the required page entry is not present in TLB, then go to the main page table get the page entry and corresponding frame number from the page table. This is called TLB miss.

And also load page entry to TLB then in the future when the same page will require by the CPU, then we do not need to access the page table again.

Note: Please continue with Effective Access Time (EMAT) at TLB hit and TLB miss: Calculate Effective Access Time (EMAT)